On November 12th, our lab member Roberto Rodriguez Zurrunero defended his PhD Thesis entitled “Dynamic Management in Operating Systems to Improve Energy Efficiency of Resource-Constrained and Wireless Devices”. This work was carried out at B105 Electronic Systems Lab under the direction of Professor Alvaro Araujo.
The thesis defense took place at the ETSI Telecomunicación in Madrid, and the work was evaluated positively earning the highest possible grade, along with the “cum laude” and international mentions.The main contributions of this PhD thesis are the following:
A proof of concept was designed and implemented to introduce a game theory algorithm in the OS scheduler meant to extend devices’ batteries lifetime.
An OS for resource-constrained devices, YetiOS, was proposed, whose main novel contribution is an adaptive engine that enhances OS’s dynamic capabilities.
A study of the cross-influences between the processing and communication tasks in an OS for resource-constrained devices was developed.
The use of an OS is introduced for a specific medical application, deep brain stimulation (DBS) devices. Four methods were proposed to reduce the power consumption overhead when introducing an OS in such devices.
It was demonstrated that in most recent resource-constrained devices with enhanced low power modes (which are used by certain OSes’ power management modules), a lower clock frequency does not necessarily imply a lower power consumption (contrary to what was stated to date in the literature). Therefore, a novel adaptive frequency-scaling algorithm (based on a well-known machine learning algorithm) was proposed to dynamically change the clock frequency to the best value in terms of power consumption.
And, finally, this is the list of peer-reviewed journal and conference publications that were obtained during the course of this PhD:
International journal articles:
R. Rodriguez-Zurrunero and A. Araujo, “Adaptive frequency scaling strategy to improve energy efficiency in a tick-less Operating System for resource-constrained embedded devices,” Future Generation Computer Systems, vol. 124, pp. 230-242, 2021.
R. Rodriguez-Zurrunero, A. Araujo, and M. M. Lowery, “Methods for Lowering the Power Consumption of OS-Based Adaptive Deep Brain Stimulation Controllers,” Sensors, vol. 21, iss. 7, 2021.
R. Rodriguez-Zurrunero, R. Utrilla, A. Rozas, and A. Araujo, “Process Management in IoT Operating Systems: Cross-Influence between Processing and Communication Tasks in End-Devices,” Sensors, vol. 19, iss. 4, 2019.
R. Pita, R. Utrilla, R. Rodriguez-Zurrunero, and A. Araujo, “Experimental Evaluation of an RSSI-Based Localization Algorithm on IoT End-Devices,” Sensors, vol. 19, iss. 18, 2019.
R. Utrilla, R. Rodriguez-Zurrunero, J. Martin, A. Rozas, and A. Araujo, “MIGOU: A Low-Power Experimental Platform with Programmable Logic Resources and Software-Defined Radio Capabilities,” Sensors, vol. 19, iss. 22, 2019.
R. Rodriguez-Zurrunero, R. Utrilla, E. Romero, and A. Araujo, “An Adaptive Scheduler for Real-Time Operating Systems to Extend WSN Nodes Lifetime,” Wireless Communications and Mobile Computing, vol. 2018, 2018.
G. Mujica, R. Rodriguez-Zurrunero, M. Wilby, J. Portilla, A. B. R. González, A. Araujo, T. Riesgo, and J. J. V. Díaz, “Edge and Fog Computing Platform for Data Fusion of Complex Heterogeneous Sensors,” Sensors, vol. 18, iss. 11, 2018.
International conference proceedings:
R. Rodriguez-Zurrunero, F. Tirado-Andres, and A. Araujo, “YetiOS: an Adaptive Operating System for Wireless Sensor Networks,” in 2018 IEEE 43rd Conference on Local Computer Networks Workshops (LCN Workshops), 2018, pp. 16-22.
As a part of his PhD, our colleague Roberto Rodriguez has started a research visit in UCD’s Neuromuscular Systems Lab, headed by Professor Madeleine Lowery. This research group is focused on the study of the human nervous system as it relates to movement, in health and disease.
During the 3-4 months of the reasearch visit, Roberto will be working in the study of closed-loop Deep Brain Stimulation devices from an electronic systems engineer perspective. The main goal is to find out novel approaches to solve current issues related to closed-loop DBS electronic devices.
We hope we could take advantage of this research visit to find synergies between B105 and UCD Neuromuscular Systems Lab!
Recently, B105 Electronic Systems Lab has designed and implemented a new low power electromyography (EMG) acquisition device. It could have only some milliwatts of power consumption while continuously acquiring samples from 4 channels at up to 800 Samples/s and processing them with an embedded high-end low-power microcontroller.
We are still fully testing and characterizing the device, but preliminary results are promissing and we expect to be able to reduce the power consumption to microwatts level by implementing new low power strategies in the device firmware.
The radar platform developed in B105 Electronic Systems Lab contains a microcontroller which process the I and Q signals adapted from the radar transceiver in order to obtain targets information -speed and distance-. The microcontroller used is a low-power STM32L496 that has a DSP module and enough RAM to perform processing tasks. It runs at 48 MHz and has low-power mode, which allows using our platform in battery-powered Wireless Sensor Networks applications.
The software developed in the microcontroller uses the YetiOS operating system which has also been developed in B105 Electronic Systems Lab and is based on well-known FreeRTOS. The architecture of the radar processing module is composed by two tasks:
Acquisition and Generation Task. This task is responsible of taking samples from the ADC and generating signals using the DAC synchronously. Both acquisition and generation is done using DMA, so other tasks -such as processing one- could run while taking samples.
Processing Task. This task provides the processed information -speed and distance of targets- to the final user. The acquired signal is filtered so the information in undesired frequency bands is eliminated. Besides, a Fast Fourier Transform (FFT) is performed in order to obtain the signals in the frequency domain. Then an OS-CFAR algorithm is applied to select the frequency peaks corresponding to targets, and the targets are selected based on signal levels and SNR ratio.
We have tested the complete radar system in real scenarios and we can process each 128 samples signal in 15 ms. That means that our radar sensor provides distance and speed information with a rate higher to 60 samples per second.
Finally, we have developed an user interface which allows us testing different configuration and the behaviour of the radar sensor on different scenarios.
Low-cost radar transceivers such as RFbeam ones allows using radar sensors in several applications where cost is an important constraint. However they need a hardware platform to work properly. Therefore, in B105 Electronic Systems Lab we have designed and implemented a hardware platform that allows obtaining using radar sensors in Doppler operating mode and FMCW operating mode.
The platform developed is low-sized and resource-constraint which allows using it in Wireless Sensor Networks applications in battery powered nodes. The hardware modules of the designed system are described below:
Power Source. Probably one of the most importan parts of the system as it must provide power to the radar transceiver and to the analog adaptation modules. The power source must provide 12 V, 5 V and 3.3 V for proper radar operation, and these sources must be highly noiseless to enchance radar performance.
Radar Transceiver. The main component of the radar sensor is the transceiver which sends and receive radar signals. K-LC5 and K-LC6 radar transceivers from RFbeam may be used, providing I and Q IF signals, and a VCO pin for FMCW operation.
Signal Adaptation Module. Signal adaptation is necessary to process radar I and Q signals and obtain information from them. An amplification stage, a low-pass filter and a high-pass filter are used in this module. Besides, a single-ended to differential stage is also used to improve signal acquisition.
Signal Acquisition. An ADC is used to digitalize the analog signals so they can be processed. The ADC used can be sigma-delta or SAR, with the higher resolution possible (12 to 16 bits), and with speeds from 10 KHz to 1 MHz. In our platform, the acquisition is done by the main microcontroller.
Signal Generation. A DAC is used to generate the signals to modulate the radar transceiver through its VCO pin. Besides, an adaptation stage is implemented to provide adequated modulation signals to the radar transceivers. The DAC used in our platform is integrated in the main microcontroller.
Processing Unit. A microcontroller is needed to process the acquired signals and obtain information from them. In our design a low-power STM32L496 microcontroller is used.