Design, implement and verify in vitro the control firmware of a neurostimulator that elicits localized neuronal responses for a thalamic visual prosthesis.
Posted on by Pablo Sarabia Ortiz
Design, implement and verify in vitro the control firmware of a neurostimulator that elicits localized neuronal responses for a thalamic visual prosthesis

Introduction

Achieving precise and localized neuronal stimulation is one of the main challenges in neurotechnology. Current approaches often suffer from low spatial specificity, which can lead to unintended activation of surrounding tissue and reduced therapeutic efficiency. A method capable of eliciting spatially localized responses would represent a significant advancement, allowing more targeted interventions, minimizing side effects, and enabling the development of high-resolution neuroprosthetic systems.

Keywords

Brain-Computer Interface (BCI), Visual prosthesis, Lateral geniculate nucleus (LGN),
Neurostimulator, Beamforming, Temporal Interference Stimulation (TIS), Deep brain stimulation
(DBS), Firmware, Neurotechnology, In vitro.

Objective

The objective of this master’s thesis is to design, implement, and verify in vitro the control firmware for a neurostimulator capable of producing localized neuronal responses. This work is framed within the VISNE project, which seeks to advance thalamic visual prostheses. The strategy explored combines two advanced stimulation techniques: beamforming and temporal interference stimulation (TIS), both aimed at improving spatial precision and overcoming the low specificity of conventional neurostimulation.

Electrode Setup for In Vitro Measurement

Testing Electrode Setup

Solution

Experimental Setup for electrode stimulation tests
The experimental setup for in vitro verification

To achieve this, a programmable four-channel neurostimulator was used. The device can generate multiple synchronized waveforms, including biphasic and sinusoidal signals, enabling the shaping of the electric field inside neural tissue. First, computational simulations of beamforming and TIS were performed to predict how stimulation patterns could be steered toward specific regions. Then, in vitro experiments were conducted using the neurostimulator and a custom experimental setup to validate these methods.

Results

The results showed strong spatial correlations between simulations and experimental measurements, confirming that both beamforming and TIS can focus electrical stimulation effectively. However, challenges were found in reproducing field amplitudes with high accuracy, as statistical analyses (MAE, RMSE) revealed residual errors in the measurements. Among the two techniques, TIS proved particularly promising, successfully generating low-frequency interference envelopes with strong spatial selectivity.

Temporal Interference results comparison with simulation

TFM: Design and evaluation of electromyography signal processing techniques using resource-constrained devices
Posted on by Pablo Sarabia Ortiz

On July 15, 2020, the master student Pablo Sarabia Ortiz read and defended his master thesis entitled “Design and evaluation of electromyography signal processing techniques using resource-constrained devices”. This master thesis is enclosed in the current B105 Electronic Systems Lab research topic of acquiring and processing electromyography (EMG) signals on the human body to achieve a wearable health device based on EMG signals.

Surface electromyographic (sEMG) is an acquisition technique based on recording muscles potential over the skin. sEMG based devices have a wide range of application: early diagnose and treatment of neurodegenerative diseases, tracking of daily activities, rehabilitation, and adaptive training.  sEMG signals are complex and present different challenges like great amount of data, complex signals, and significant variations between subjects and days. For most of these applications is required to identify and classify the gestures or movements that the user is doing. This classification is a task that requires great amount of resources (memory and CPU). This thesis is focused in understanding the sEMG signal characteristics and designing a classifier for hand gestures, by using the custom acquisition board.

Picture of the hardware used for sEMG acquisition. On the left the electrodes, on top of the image a preamplifier and on the bottom right corner the stack of PCBs composed of the microcontroller and the ADC.
Picture of the hardware used for sEMG acquisition. On the left the electrodes, on top of the image a preamplifier and on the bottom right corner the stack of PCBs composed of the microcontroller and the ADC.

First, a quantitative analysis of the sEMG data was carried out by using parallel factor analysis (PARAFAC). The dataset used was NINAPRO, because it contains numerous different hand gestures performed by different subjects in different days. This PARAFAC analysis showed that is possible to reduce the number of channels from 16 to 4 without significant loss of information, as shown in the figure below. It also showed that most of the information is under the 350 Hz range. PARAFAC proved to be an interesting method for choosing the most significant channels in the dataset.

Process followed to do the PARAFAC analysis of the data from the NINAPRO dataset.
Process followed to do the PARAFAC analysis of the data from the NINAPRO dataset.

Second, an acquisition system to log the data to the computer was established. This acquisition system had 4 channels at a sampling rate of 500 Hz each. The data once logged was formatted and stored using MATLAB. Eight different gestures were performed, as shown in the figure. Then a support vector (SVM) machine classifier was trained obtaining an 99% accuracy in cross validation.

Table with all the gestures recorded for the master thesis.
Table with all the gestures recorded for the master thesis.

Third, a two level three variables factorial design was carried out to model the influence of the design variables in three features of the classifier (execution time, memory footprint and accuracy). The three design variables studied were: codification of the SVM, data precision (float32 or float64) and length of the sample. The results shown that float64 should never be used, and that there is always a tradeoff between classifier accuracy versus the memory footprint and speed of the classifier. It was also identified the memory footprint as the bottleneck for the use of the classifier in a resource-constrained device. It was achieved a reduction of 1/14 of the original memory footprint and a speedup of 233 times, however accuracy of the classifier lowered to 85%.